Verilog- Operator, operand, expression and control - презентация

Verilog - Operator, operand, expression and control - Ando KI

Contents Expression Operand Operator Bitwise and reduction operators Concatenation and replication example Sign example Shift example Expression bit-length Bit-length example Conditional statements if-else/if-else-if case Looping statements forever example repeat example while example for example

Verilog expression Verilog expression combines operands with operators to produce a result. Scalar expression results a scalar (single-bit) result. The least significant bit of the result is used when the expression results in multi-bit.

Verilog operand signed and unsigned constant An integer with no base specification shall be a signed value in 2’s complement form. 12 and -12 An integer with an unsigned base specification shall be interpreted as unsigned value. ‘d12 -’d12 == -32’d12 == FFFFFFF4 Sign base should be used for signed integer. -’sd12 or –’SD12

Verilog operator (1/2)

Verilog operator (2/2) Logical operators: &&, ||, ! Result in one bit value Bitwise operators (infix): &, |, ~, ^, ~^, ^~ Operation on bit by bit basis Reduction operators (prefix): &, |, ^, ~&, ~|, ~^ Result in one bit value Logical shift operators: >>, << Result in the same size, always fills zero Concatenation operators: {, } Replication: {n{X}} Relational operators: >, <, >=, <= Result in one bit value Logical equality operators: ==, != Result in either true or false Case equality operators: ===, !== Exact match including X/x and Z/z Conditional operators: ? : Like 2-to-1 mux Arithmetic/math operators: +, -, *, /, % If any operand is x the result is x. Unary: +, -

Bit-wise and reduction operators

Concatenation and replication example ‘code/verilog/expression/replicate’ example.

Sign example (1/2) ‘code/verilog/expression/sign’ example.

Sign example (2/2) ‘code/verilog/expression/sign’ example.

Shift example ‘code/verilog/expression/shift’ example.

Expression bit-length The Verilog uses the bit length of the operands to determine how many bits to use while evaluating an expression.

Bit-length example ‘code/verilog/expression/bitlength’ example.

Bit-length example

Conditional statement: if-else/if-else-if The conditional statement (if-else or if-else-if statement) is used to make a decision about whether a statement is executed. If the expression evaluates to true (that is, has a nonzero known value), the first statement shall be executed. If it evaluates to false (that is, has a zero value or the value is x or z), the first statement shall not execute. If there is an else statement and expression is false, the else statement shall be executed.

Case statement The case statement is a multiway decision statement that tests whether an expression matches one of a number of other expressions and branches accordingly. The default statement shall be optional. In a case expression comparison, the comparison only succeeds when each bit matches exactly with respect to the values 0, 1, x, and z. The bit length of all the expressions shall be equal so that exact bitwise matching can be performed. Don’t care cases ‘casez’ treats z or ? symbols in the expression or case items as don’t-cares. ‘casex’ treats z or x or ? symbols as don’t-cares.

Looping statements forever Continuously executes a statement. repeat Executes a statement a fixed number of times. If the expression evaluates to unknown or high impedance, it shall be treated as zero, and no statement shall be executed. while Executes a statement until an expression becomes false. If the expression starts out false, the statement shall not be executed at all.

Forever example ‘code/verilog/expression/forever’ example.

Repeat example ‘code/verilog/expression/repeat’ example.

While example ‘code/verilog/expression/while’ example.

For example ‘code/verilog/expression/for’ example.