ESD Class 0 Protection Stress Levels презентация

ESD Class 0 Protection Stress Levels Their Origin and Application José D. Sancho

ESD Event Classification From EMI to EOS - Speed Classification EMI caused ESD has short and repetitive pulses with low energy. EOS is and ESD event with unlimited Current/Time constrains HBM, MM & CDM model typical events in the manufacturing areas.

Introduction 1What is an ESD Sensitivity Level? 2How is it obtained? 3Why is it important to the user? 4Why different test models?

Overview ESD Models Provide a way to characterize the sensitivity of components to ESD The different ESD models simulate the different environments experienced by electronic components during the manufacturing process. Parts and assemblies may be exposed to more than one type of ESD event over the manufacturing and test life cycle.

Purpose of ESD Models Models establish Benchmarks for ESD Sensitivity. Different Models are used to simulate different work environments. Models provide help to prevent and analyze ESD Failures

ESD Event Test Models Human Body (HBM): discharging event through the body and the part to ground. Machine (MM): discharge voltage through automated handling equipment or hand-tools and the part to ground. Charged Device (CDM): discharge into or out of a part due to charge accumulation within the part itself.

ESD Damage to Die Structure Damage types can vary depending on event models. Long, higher Voltage HBM event can look like electrical overstress at die periphery. Fast, high Current CDM event causes defects in core area which can be latent failures. Must use advanced FA techniques to locate sites. A Comparison of Electrostatic Discharge Models and Failure Signatures for CMOS Integrated Circuit Devices, M. Kelly, G. Servais, T. Diep, S. Twerefour, D. Lin, G. Shah, EOS/ESD Symposium 95

ESD Sensitivity Levels

Models Comparisons

ESD Models vs. Sources of Threats

“Class 0” Parts Protection “Class 0” has become the generic term to define parts which are very sensitive to ESD. It now encompass parts sensitive to HBM <250v as well as parts damaged by EMI Sensitivity for these parts needs to be also defined using CDM classifications. {EPAs as currently implemented at GSFC can protect parts sensitive to ~100 V HBM}

Model Implementation NASA-HDBK-8739.21 (in Approval Cycle) Guide for Creating an ANSI/ESD S20.20 Implementation Plan Focus is on HBM: emphasis on operator grounding, dissipative surfaces, reduction of triboelectric charging For HBM & MM the methods for protective practices and creating protective spaces are highly reproducible and “low tech” Proper implementation requires training and follow-up HBM safety methods have brought HBM & MM failures down (now are ~10% of failures encountered industry-wide)

Model Implementation Recent failures of high speed devices (LVDS, FPGAs) drive users to Class 0 HBM… …But IC manufacturers calculate that about 90% of the failures from the field are due to CDM ESD events. CDM-related field returns are associated with low, medium, and high sensitivity devices. Safety methods for CDM are highly customized because the model is less mature (many unknown variables and variable relationships, rapidly changing characteristics

Class 0 & CDM Class 0 refers to the HBM model Currently most ESD damage is caused by much shorter pulses best defined in the CDM model. ESD pulses can be clamped by internal shunts and bypasses at the expense of design complexity and speed. There is a limit beyond which the device cannot be internally protected.

Limits of Design-in Protection CDM protection by the design is driven by the peak current from the IC package discharge at the CDM voltage targeted. The larger the package the higher the peak current of the CDM pulse created. The smaller the geometry of the circuit the lower the breakdown voltage of the circuit Present Theoretical Limit ≈ 125v CDM

Protection of Devices Sensitive to Class 0 ESD “Shalls” related to HBM Class 0 protection: Dissipative chairs and stools Conductive or dissipative floors or floor mats Relative humidity Ionizers Smocks Procedures for Mating and de-mating of harnesses Soldering iron testing Signage

External ESD Control Measures for Extremely Sensitive Devices

Charged Board Events CBE are caused when a board is pulled from the bag and place on a conductive surface This ESD hazard was often overlooked During FA the components failure is usually classified as EOS damage. Recent data reported by several Companies indicates that CBEs are commonly missed in FA

Where to Get More Information WEB searches under “ESD Models” ESDA publications Consulting services provide Advice on tough ESD problems and Solutions.

References ANSI/ESD STM5.1-2001 ESD Sensitivity Testing (HBM) ANSI/ESD STM5.2-1999 ESD Sensitivity Testing (MM) ANSI/ESD STM5.3.1-1999 ESD Sensitivity Testing (CDM) ANSI/ESD SP5.2.2-2004 ESD Sensitivity Testing (SDM) ANSI/ESD SP5.5.1-2004 ESD Sensitivity Testing (TPL) Scott M. Hull, “ESD Failures in Thin-Film Resistors” NASA/Goddard Space Flight Center http://esdsystems.com/whitepapers/ http://www.semiconfareast.com http://www.ce-mag.com/archive/01/09/henry.html http://www.ce-mag.com/ce-mag.com/archive/01/03/0103CE_046.html White Paper: Industry Council on ESD Target Levels on CDM http://ossma-dev.gsfc.nasa.gov/ESDResources/index.php https://ossmacm.gsfc.nasa.gov/

Thank you Any Questions?

Typical HBM Generated Failures

Typical MM ESD Stress Failure

Typical CDM generated failures

Typical CDM Generated Failure